In integrated circuit (IC) devices, current non-planar NAND memory architecture uses recessed shallow trench isolation (STI) to form FinFET-like memory cells to overcome planar NAND scaling barrier beyond 45 nm technology node. However, the nitride storage layer for the FinFET-like cell contacts the STI oxide material, which raises a charge retention concern when the nitride storage layer is conducting. Accordingly, it would be desirable to provide an improved non-planar memory cell and method of manufacturing thereof absent the disadvantages discussed above.